How about a verilog case statement that covers a range?

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SystemVerilog has it using the inside operator

case (xcount) inside
   : junk<=1; 
  101 : junk<=2; 
   : junk<=3; 
endcase

Another nice thing about the case inside statement is that it uses asymmetric wildcard matching.

case (xcode) inside
  3'b00? : junk<=1; 
  3'b0?0 : junk<=2; 
  3'b?00 : junk<=3;
  default: junk <='x;
endcase

That means don't cares only match on the case item, not the selecting expression. So if xcode == 3'bx01, the default branch would be taken, not the first branch.

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I added this syntax to an existing SystemVerilog design, but Quartus choked on the "inside" keyword when I tried to build. It's a little ironic, because the Quartus text editor recognizes it as a key word (it shows up in blue). Am I correct in saying that Quartus does not support "case inside"? I do not see it mentioned in the Quartus SV Support documentation.