How about a verilog case statement that covers a range?

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Yes. Hopefully if more people ask for it, it will become more widely supported.

To code this in Verilog, you could create an in-between function or macro

function reg inbetween(input  low, value, high); 
begin
  inbetween = value >= low && value <= high;
end
endfunction
case (1);
  inbetween(1,xcount,100): junk<=1;
  inbetween(101,xcount,101): junk<=2;
  inbetween(102,xcount,200): junk<=3;
endcase

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Thanks dave. Yes, I think this is very good idea. And this should be able to be synthesized, right?