Hola All, I recently made a vhd file from scratch that tested some simple logic circuits successfully. All I have had as resources in this task is the tutorial files from ModelSim (counter.vhd, and tcounter.vhd), and a single text on vhdl (Circuit Design with VHDL by Peroni). Things were looking good until I attempted to make and test a frequency divider. http://sphotos.ak.fbcdn.net/hphotos-ak-snc4/hs148.snc4/36780_10150214314760055_754135054_13023800_1551964_n.jpg This frequency divider has one input (clk) and two outputs (out1, and out2). The code for this divider is below as well as the testbench I made for it. The problem is I get an undefined signal coming out of both my outputs. Any explanation as to why would be much appreciated. Thanks for the assist, Triston ****************************Freq Divider code******************************* Library ieee; Use ieee.std_logic_1164.all; ------------------------------------> Entity Freq_Div_1 is Generic(n : integer := 4); Port( clk : IN std_logic; out1,out2 : buffer std_logic ); End Freq_Div_1; ------------------------------------> Architecture Div of Freq_Div_1 is Signal count1 : Integer Range 0 to 7; Begin Process (clk) Variable count2 : integer range 0 to 7; Begin if (clk'EVENT and clk='1') then count1 <= count1 + 1; count2 := count2 + 1; if ( count1 = n) then out1 <= not out1; count1 <= 0; end if; if(count2 = 2) then out2 <= not out2; count2 := 0; end if; end if; End Process; End Div; *************************** My TestBench Debacle ************************* Library ieee; Use ieee.std_logic_1164.all; -------------------------------------> Entity tFreq_Div_1 is Port( out1,out2 : buffer std_logic ); End tFreq_Div_1; -------------------------------------> Architecture testBench of tFreq_Div_1 is -- ******** Component ******** -----> Component Freq_Div_1 Port( clk : in std_logic; out1,out2 : buffer std_logic ); End Component Freq_Div_1; --**** Test Signals ******* --------> Signal clk : std_logic :='0'; -------------------------------------> Begin dut:Freq_Div_1 Port MAP ( clk => clk, out1 => out1, out2 => out2 ); clk_In : Process Begin wait for 10 ns; clk <= not clk; End Process clk_In; intialize : process begin wait for 1 ns; out1 <= '0'; wait for 1 ns; out2 <='0'; wait; End process intialize; End testBench;

Hi. I did not read the test bench, found a bugg in the main file. When you do not initiate a signal/variable is starts as undefined. In your declarations, try to end the line with ":=0" e.g. the port: out1,out2 : buffer std_logic := '0' the counters: Signal count1 : Integer Range 0 to 7 := 0; Variable count2 : integer range 0 to 7 := 0; that should solve it.

Hint: An easy way to generate a clock in testbenches is: clk <= not clk after 5 ns; -- generate a 100 MHz clock (don't forget to initiate the clock to e.g. '1') This reduces the number of lines for the clock generation to one short line, and increases the readability.

Thanks for the suggestion Peter. However, this didn't solve the issue. Moreover, the previous testbech's I wrote (the ones that gave me all the false hope), didn't have initializations for the output. The output was realized solely by the component under test. Perhaps I should practice with more concurrent code and more slowly work my way into sequential code - bummer.

You shouldn't drive the outputs. You are meant to get them driven by your DUT. Only use clk stimulus. Also never use the buffer port. This is garbage of VHDL HISTORY THAT LURKS IN UNIVERSITIES - WITH RESPECT. Note also the testbench entity name should be unique and doesn't need external interface e.g. entity fre_div_tb is end entity; then call up the DUT as a component

Kaz, thank you , thank you , thank you! I am seeing exactly what I expected to see after I got rid of the external interfaces in the entity name, and placed the two additional signals in the declaration of the architecture (out1, out2) and viola - happy! However, I tried to get rid of the buffer , and replaced it with out, but this didn't work. I got errors because in the Freq_Div_1 code I have out1 <= not out1; and out2 <= not out2;, and this requires these two ports to be read, hence the buffer. If this is "garbage" what would be the alternative? Again, thanks for the help. Triston

Altera_Forum

Honored Contributor

15 years ago

Homemade TestBench attmept

Hola All,

I recently made a vhd file from scratch that tested some simple logic circuits successfully. All I have had as resources in this task is the tutorial files from ModelSim (counter.vhd, and tcounter.vhd), and a single text on vhdl (Circuit Design with VHDL by Peroni). Things were looking good until I attempted to make and test a frequency divider.

http://sphotos.ak.fbcdn.net/hphotos-ak-snc4/hs148.snc4/36780_10150214314760055_754135054_13023800_1551964_n.jpg

This frequency divider has one input (clk) and two outputs (out1, and out2). The code for this divider is below as well as the testbench I made for it. The problem is I get an undefined signal coming out of both my outputs. Any explanation as to why would be much appreciated.

Thanks for the assist,

Triston

****************************Freq Divider code*******************************

Library ieee;

Use ieee.std_logic_1164.all;

------------------------------------>

Entity Freq_Div_1 is

Generic(n : integer := 4);

Port(

clk : IN std_logic;

out1,out2 : buffer std_logic

);

End Freq_Div_1;

------------------------------------>

Architecture Div of Freq_Div_1 is

Signal count1 : Integer Range 0 to 7;

Begin

Process (clk)

Variable count2 : integer range 0 to 7;

Begin

if (clk'EVENT and clk='1') then

count1 <= count1 + 1;

count2 := count2 + 1;

if ( count1 = n) then

out1 <= not out1;

count1 <= 0;

end if;

if(count2 = 2) then

out2 <= not out2;

count2 := 0;

end if;

End Process;

End Div;

*************************** My TestBench Debacle *************************

Library ieee;

Use ieee.std_logic_1164.all;

------------------------------------->

Entity tFreq_Div_1 is

Port(

out1,out2 : buffer std_logic

);

End tFreq_Div_1;

------------------------------------->

Architecture testBench of tFreq_Div_1 is

-- ******** Component ******** ----->

Component Freq_Div_1

Port(

clk : in std_logic;

out1,out2 : buffer std_logic

);

End Component Freq_Div_1;

--**** Test Signals ******* -------->

Signal clk : std_logic :='0';

------------------------------------->

Begin

dut:Freq_Div_1

Port MAP

(

clk => clk,

out1 => out1,

out2 => out2

);

clk_In : Process

Begin

wait for 10 ns; clk <= not clk;

End Process clk_In;

intialize : process

begin

wait for 1 ns; out1 <= '0';

wait for 1 ns; out2 <='0';

wait;

End process intialize;

End testBench;

12 Replies

Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
The alternative is this:

declare out1_int and out2_int as signals. do your read/drive then wire up out1 port to out1_int...

You now can see what buffer is doing, it is meant to bypass the double work but causes confusion since it is meant to be output only (not input) but that can be read internally ???
Future vhdl is meant to allow reading output ports without declaring them as buffer.
--- Quote End ---

I'm waiting for that new VHDL standard. It's just silly to not be able to read the output port, I think. But I still don't get why you should not use the buffer syntax? Except for the "tradition" for not using it, why is it not used by experienced?
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
I'm waiting for that new VHDL standard. It's just silly to not be able to read the output port, I think. But I still don't get why you should not use the buffer syntax? Except for the "tradition" for not using it, why is it not used by experienced?
--- Quote End ---

Be prepared to wait a while. Vendors can be really slow at adding new standards to products. I know altera have started to support 2008, but only parts of it, and mentor hardly support any of it yet (which means being safely able to write 2008 compliant code isnt going to happen for a while).

As for the out port question - I think you're looking at it from the wrong angle. VHDL does not have formal "parts" like register, tri-state buffers, multipliers etc. It is all implied using behavioural code. Therefore an out port is simply that - an output. It is the process that actually implements the register.

I think thats why buffer is hardly used - it doesnt really fit in with the rest of the language.

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Homemade TestBench attmept

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