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I'm waiting for that new VHDL standard. It's just silly to not be able to read the output port, I think. But I still don't get why you should not use the buffer syntax? Except for the "tradition" for not using it, why is it not used by experienced?
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Be prepared to wait a while. Vendors can be really slow at adding new standards to products. I know altera have started to support 2008, but only parts of it, and mentor hardly support any of it yet (which means being safely able to write 2008 compliant code isnt going to happen for a while).
As for the out port question - I think you're looking at it from the wrong angle. VHDL does not have formal "parts" like register, tri-state buffers, multipliers etc. It is all implied using behavioural code. Therefore an out port is simply that - an output. It is the process that actually implements the register.
I think thats why buffer is hardly used - it doesnt really fit in with the rest of the language.
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