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Altera_Forum's avatar
Altera_Forum
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15 years ago

Homemade TestBench attmept

Hola All, I recently made a vhd file from scratch that tested some simple logic circuits successfully. All I have had as resources in this task is the tutorial files from ModelSim (counter.vhd,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You shouldn't drive the outputs. You are meant to get them driven by your DUT. Only use clk stimulus.

Also never use the buffer port. This is garbage of VHDL HISTORY THAT LURKS IN UNIVERSITIES - WITH RESPECT.

Note also the testbench entity name should be unique and doesn't need external interface e.g.

entity fre_div_tb is

end entity;

then call up the DUT as a component