Hold violation on source synchronous clocks

Thanks for your response and for your excellent user guide.

The path is not inside a DSP block. The thing is, I'm not sure if I need to over constrain it. The DSP block is running at the slower 20MHz clock and then the result is valid once every 50 clocks of the 20MHz clock. and then the result needs to be clocked into the faster system clock at 100 MHz. So I'm using the data valid as a clock enable but I'm trying to figure out if that means that it's safe to relax both the setup and hold constraints?

Also, do I need to extend the data valid (clock enable) to be asserted for the entire width of the expanded window?