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Altera_Forum's avatar
Altera_Forum
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9 years ago

Hold violation on source synchronous clocks

Timing is failing with Hold time negative slack of (-0.098) when going from a 20MHz to a 100MHz clock domain (both clocks are synchronous and generated from the same PLL). This is a cyclone V design...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I suggest to try the routing optimizations for hold timings if you have sync registers between the clock domains.

In my previous post I meant to use clock enable in the 100MHz domain synced to the negative edge of the 20MHz, thus you'll have 2/20MHz delay. However, this is a functional change and I don't know if it would have some impact on your design.

Thanks,

Victor