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Altera_Forum
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11 years ago

Hold Violation inside ram_block - what is going on?

Hello, In my design I have a DCFIFO, which I use to get data across two clock domains. The clocks are the same frequency (143.25MHz), but may be out of phase, and there may be jitter with there...
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Altera_Forum
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11 years ago

Sebastion,

I am seeing the somewhat the same thing. I have inferred a Simple Dual Port RAM. Writes on Port A, Reads on Port B. Only one clock in this area of logic (200 MHz). TimeQuest flags a setup error between PORT_B_WRITE_ENABLE_REG and logic latching the RAM's output data. I have looked at the instantiation in Technology Viewer and Port B does not use a Write Enable (register is grayed out).

I'm tempted to just ignore this (or declare it a False Path) and treat it as a disconnect between Quartus and TimeQuest.

Did you ever find a reason for this behavior?