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Altera_Forum's avatar
Altera_Forum
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16 years ago

Hold time violations in simple clock divider

I am using a register to divide a 100 MHz input clock and am getting hold time violations. The actual code is a tad more complicated (it switches to a slower clock divider depending on an input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

But according to what the OP is saying, he is getting hold violation at the clock generation itself, not on registers using the generated clock. This should not happen, let alone on a register feeding itself.