Hold time violations in simple clock divider

@wcalkins,

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I am using a register to divide a 100 MHz input clock and am getting hold time violations.

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making your own clock in this way is not considered good design practice. It is normal that your timing verifier runs into the problems you mention.

Do not use gated or derived clocks to control flip-flops, registers and memories in your design. In case you need a slower or faster clock, use a PLL to make this clock.