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If your output data and clock go together from FPGA then you need to set output delays as follows:
max delay = +tSU = +10 ns
min delay = - tH = -10 ns
ignoring board effect
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unfortunately, the clock is not generated by fpga, it was determined outside.
i have to set max delay larger than 10ns and min delay smaller than -10ns.
dose quartus set half period as default sample window?
can i change that value?
the typical tSU of external chip is 24ns and tH is 12ns, i think it would be easy to satisfy those requirement.
because there is only one output register before output pin(see attachment:register2output)
and the setup slack is still very large.(setup.jpg)
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