hold time violation

i find a para of text in Quartus handbook 10.1 in P13-6

"When you turn on Optimize Hold Timing ...... the Fitter works to meet the following criteria:

■ Hold times (tH) from device input pins to registers

■ Minimum delays from I/O pins to I/O registers or from I/O registers to I/O pins

■ Minimum clock-to-out time (tCO) from registers to output pins"

the second criteria only shows that fitter would minimum the delay between register and pins.

but in the case above, it would not a right method.

is it a bug or my misunderstanding?