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Altera_Forum's avatar
Altera_Forum
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15 years ago

hold time violation

when i synthesis & fit my design, hold time violation is reported at my output port in fast model timing analysis. the fpga was connected with some slow device, which requires a relative large hol...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If your output data and clock go together from FPGA then you need to set output delays as follows:

max delay = +tSU = +10 ns

min delay = - tH = -10 ns

ignoring board effect