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Altera_Forum's avatar
Altera_Forum
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14 years ago

hold time violation

hi, when i tried to make a timing analysis for my design, i get a hold time violation between two nodes.. i attached a screenshot of the error. actually it is not an error, but probably it is t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

hi,

actually i'm using two clocks in my design..but those two clocks are generated by the FPGA boad(i'm using cyclone II which provides two frequency values :28MHz and 50MHz), so i'm not using gated clocks.