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NSuku1's avatar
NSuku1
Icon for New Contributor rankNew Contributor
7 years ago

HLS not generating the VHDL output

Hi, I designed a matrix block using Intel HLS and compiled.. But why does it generate the Verilog output instead of VHDL ? How to make it to generate the VHDL output? Please help me. Thanks, Ni...
HRZ's avatar
HRZ
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Intel's OpenCL and HLS compilers have always been generating verilog as their output. I think adding an option for VHDL was in their roadmap somewhere along the lines but it never happened. The word "VHDL" is not used even once in any of Intel's HLS-related guides and hence, I would assume generating VHDL output is not supported.