Hinder Quartus from extracting state machines on specific register?

That would be a bit pointless, because with an enumerated type it has no encoding, and hence would not be synthesisable without extracting the state machine.

You can manually specify the encoding yourself using the enum_encoding attribute.

http://quartushelp.altera.com/14.0/mergedprojects/hdl/vhdl/vhdl_file_dir_enum_encoding.htm

Thanks for the reply.

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[...] with an enumerated type it has no encoding, and hence would not be synthesisable without extracting the state machine.

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OK. That seems like an odd limitation of Quartus synthesis though, combinatorial signals that are enumerated are obviously assigned an encoding automatically and not extracted to state machines, so I donät really see the logic behind not doing this for registers as well.

I am actually operating on an array of the enumerated type. This is the code, and the attributes I tried:

  type TselectedOperation is (op_clrSinceRead, op_usrWrite, op_avsWrite, op_none);
  signal selectedOperation : TselectedOperation; -- combinatorial, not extracted to fsm
  type TselectedOperation_array is array(0 to 23) of TselectedOperation;
  signal selectedOperation_pipe: TselectedOperation_array;
  
  attribute enum_encoding : string;
  attribute enum_encoding of selectedOperation_pipe(0) : signal is "00 01 10 11"; -- 1. Quartus error
  attribute enum_encoding of selectedOperation_pipe: signal is "00 01 10 11"; -- 2. still fsm's on selectedOperation_pipe

With 1. above, I get:

Error (10612): VHDL attribute error at avsRegMap.vhd(50): Attribute Specification contains illegal name

With 2. above, Quartus still infers 23 fsm's for the elements of the array (I'm not surprised, I'm assigning enum_encoding to an array, not to a signal representing a register.)

Any idea how to attach the attribute in this case, to see if it helps preventing extracting fsm's?

I still dont quite know what you are looking for. A state machine is nothing more than a load of gates and registers, and you code must map to gates and registers at some point.

The problem with enumerated types is they do not directly map to 0's and 1's, hence all the different options Quartus gives for mapping them to different encoding methods. By default, if there are more than 3 states, it will use 1 hot, and for less than 3 states, it will use 00, 01, 10 etc.

Enumerated types are most commonly used in FSMs. For anything else, people tend to use explicit signals. What is selectedOperation? where does it come from? it must map to something? enumerated types are used where it doesnt map to anything, and you want to synthesisor to map it for you.

There is the possibility of simulation confusion with selectedOperation. THe default value will be op_clrSinceRead. If you used a std_logic_vector, it would default to "UU" which may indicate a problem somewhere.

I does seem that this:

attribute enum_encoding of selectedOperation_pipe(0) : signal is "00 01 10 11"; -- 1. Quartus error

May be an error. I suggest raising it with altera mysupport, but if you are just using it as a pipeline, then you would need the same encoding for the entire pipeline, and not change the encoding part way through the pipe.

SO what is your reason for not wanting encoding on your enumerated type?