Hierarchical Name Reference in QII

Hi,

I'm trying to get signals out of my modules for debug, and I don't want to route them through 50 levels of hierarchy, I just want to reference them in my top module. BUT, it doesn't work in QII! isn't it a basic Verilog syntax?

here's what I do:

----------------------------

A a_inst(...);

assign debug = a_inst.<some internal signal>;

----------------------------

The error I get is at synthesis time (not fitter):

----------------------------

Error (10207): Verilog HDL error at ...(...): can't resolve reference to object "..."

----------------------------

Any help is appreciated.