Altera_Forum
Honored Contributor
16 years agoHiding VHDL code (Black Box)
Hi,
I am currently working for a company where there are two different departments doing two different major blocks of the design. Anyway we are getting close to the integration phase and my boss is telling me that we cannot show our source code to the other department and from what I understand they too are unwilling to show theirs. Anyway my question is, is there a way to create a component (like a black bos I think is the term) which we can provide to the other group which will prevent them from seeing our source code? Possibly this is more of a general VHDL question rather than an Altera specific one, but please forgive if the post seems a little out of place. I am unsure if Quartus would have a feature to help with this. Also, i am interested to know if this type of occurence is normal in companies where different departments act like they are competing companies. Is it normal practise in companies to hide source code between departments in anyone´s expereince? I´m not too keen on the idea myself, as I am thinking about when it come to debugging any errors, it will be difficult to know where to start if both parties do not have access to the entire sopurce code. I appreciate any tips on weather or not it is possible to incorporate a portion of a desiggn into a black box. Many thanks for the help