hi-Z sometimes shown as 0

Hello,

In Verilog

If I have (in module section):

output out_in;

parameter A=2,B=3,C=4,D=5;

reg [2:0]state;

reg out_in;

then in an always section:

if (state == D) out_in = 1'bZ; else if (state == A) out_in = 1; else out_in = 0;

then in the Waveform Editor, all the Z instances are shown as 0 (low level)?

but if I use the following instead:

out_in = (state == D) ? 1'bZ : 1; // only two conditions, I require three as described later

then in the Waveform Editor, all the Z instances are shown as Z (darker, thicker line, mid way between high and low levels).

Why is this??

If I have to use the "? :" instead of "if statements", is the following acceptable (i do not get any errors):

out_in = (state == D) ? 1'bZ : (state == A) ? 1 : 0;

as I require the "if", "else if" and "else" (three) conditions.

thank you