hi! Understanding a coding (counter), help

hi!!

I have written:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity counter is

generic (

n : integer := 4;

k : integer := 8

);

port

(

clock : in STD_LOGIC;

reset_n : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR(n-1 downto 0);

SW: in std_logic_vector(7 downto 0);

KEY : in std_logic_vector(1 downto 0);

LEDR : out std_logic_vector(7 downto 0)

);

end counter;

architecture rtl of counter is

signal Q_int: std_logic_vector(n-1 downto 0);

begin

PROCESS(clock, reset_n)

begin

if (reset_n = '0') then

Q_int<= (others => '0');

elsif ((clock'event) and (clock = '1')) then

if Q_int>= k-1 then

Q_int<= (others => '0');

else

Q_int <= Q_int + 1;

end if;

end if;

end process;

Q <= Q_int;

end rtl;

architecture Behavioral of counter is

component counter

generic

(

n : integer := 4;

k : integer := 8

);

end component;

begin

eight_bit: counter

generic map ( n => 8, k => 4)

port map eight_bit( clock, reset_n, Q, KEY(1), KEY(0), LEDR );

end Behavioral;

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is correct?? exactly I want to write:

Create a modulo-k counter by modifying the design of an 8-bit counter to

contain an additional parameter. The counter should count from 0 to k-1.

When the counter reaches the value k-1 the value that follows should be 0.

Your circuit should use pushbutton KEY0 as an asynchronous reset, KEY1 as

a manual clock input. The contents of the counter should be displayed on red

LEDs. Compile your design with Quartus II software, download your design

onto a DE1 board, and test its operation. Perform the following steps:

-Create a new Quartus II project which will be used to implement the

desired circuit on the DE1 board.