Honored Contributor
Honored Contributorok, I get it, thanks again!!
but; define a new port as Input, i have to delete Q or other port?; entity counter is generic ( n : natural := 4; ); port ( clock : in std_logic; reset_n : in std_logic; q : out std_logic_vector(n-1 downto 0)k: in unsigned (15 downto 0); ); end entity; architecture rtl ofcounter issignal value : std_logic_vector(n-1 downto 0); begin process(clock, reset_n) beginif (reset_n = ’0’) then value <= (others => ’0’); elsif ((clock’event) and (clock = ’1’)) then
if (value < k) then
value <= value + 1;
else
value <= (others => '0');
end if; end process; q <= value; end rtl;
