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Altera_Forum
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11 years ago

hi! Understanding a coding (counter), help

entity counter is generic ( n : natural := 4; ); port ( clock : in std_logic; reset_n : in std_logic; q : out std_logic_vector(n-1 downto 0) ); end entity; architecture rtl of co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It appears to be a non-standard counter (unless it's VHDL 2008). But you missed out the library inclusions, so would not compile at all.