hi! Understanding a coding (counter), help

This is a very simple piece of code:

First the Entity "counter" is declared with a Generic "n" (Kind of Parameter used for the Instance-Generating) and three Ports "clock", "reset_n" and the only Output "Q" whith the variable width of "n".

Then the Architecture:

There is one Signal "value" (Wire for Verilog-Programmers) also with the variable width of "n".

The PROCESS:

The Process listenes to "clock" and "restet_n": If "reset_n" is '0' then all bits of "value" are cleared to '0'.

If "reset_n" is not '0', then value is counted up by one if there is a rising edge on "clock".

The setting of the Output:

The Output "Q" is set to the value of "value" asynchronously.

You can also do the staight way and increment "Q" in the Process, but it is recommended not to use Outputs in a Process because you can not read from them.

For Example if you increment "value" you can use this Signal in another Process and read it out. If you increment "Q" instead, you cannot read "Q" in another Process because Output-Ports are not readable.