Hi,
It is posible to suppress DRC rule in Design Assistant for certain signal or design unit?

Question

For example for rule ACD-30023 when I know clock crossing between registers in_reg_12345 and out_reg_12345 is ok and I dont want to see this vialotion in report

meiyan_l_intel · Answer

Hi,

You can customize the design assistant for your design and report requirement by spcify the options that control the rules and parameters apply to various stage of design for DRC as below with steps below:

Click Assignments > Settings > Design Assistant Rule Settings, then search the rule name (eg: ACD-30023)

For more information, you may need to refer to Chapter 2.3 as link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf

Thanks

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Hi, It is posible to suppress DRC rule in Design Assistant for certain signal or design unit?

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