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AKohl3's avatar
AKohl3
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window.

From what i can tell the ADC module only needs a command to select which port to sample so how do i make pin assignments to confirm the ADC in use!
  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    6 years ago

    Hello there ,

    Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report.

    As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design.

    In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same.

    Hope helps ,

    Thank you ,

    Regards,

    Sree

SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Here is the screen shot of compilation report attached.

One thing I noticed that you dont have a RTL for enable the channel or reading the ADC channels , I added a test logic directly enabled the channel "0" , Channel Valid and Channel start. After that I could see in ADC resources in compilation report. I think since the implemented RTL is not using ADC /enable the ADC Quartus is optimization is not instantiating the module.

Sorry , I dont know how to attach the file here ,Here is the added logic in the top module for your reference ,

command_channel <= "00000";

command_valid <= '1';

command_start <= '1';

command_ready <= '1';

process (P_I_CLK100,response_valid)

begin

if rising_edge(P_I_CLK100) and response_valid = '1' then

data_to_display <= response_data;

end if;

end process;

Thank you,

Regards,

Sree

AKohl3's avatar
AKohl3
Icon for New Contributor rankNew Contributor
6 years ago

I added the above suggested logic but to no success. I even tried setting up a new project to double ensure the right part selection from the beginning, however I do not see the ADC module invoked neither the addition of the ADC pins in the final summary. Attached is the screenshot and top level module. I hope this is not a Quartus standard versus lite issue? And if the issue is not software related, can you send me the above depicted correctly compiled project+project files from your end?