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AKohl3's avatar
AKohl3
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window.

From what i can tell the ADC module only needs a command to select which port to sample so how do i make pin assignments to confirm the ADC in use!
  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    6 years ago

    Hello there ,

    Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report.

    As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design.

    In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same.

    Hope helps ,

    Thank you ,

    Regards,

    Sree

SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

But the design you send me as per below screen shot , with having error you wont be able to generate the HDL with error in qsys.

which one i should be believe your design files or your screen shot ? please clarify