Help:What does the TimeQuest Timing Analayzer's info mean?

Thanks very much, Brad.

Thank you for your twice explanation for the ripple clock for me .

I find you understand my design well . Clk1 is an output port being used as a clock in my design , it is 16-divided by clk, i use some combinational logic to control clk1 in order to make clk1 and datain synchronize , datain is steady while the phase of clk1 can change arbitrary.

After reading your posts , i have realized the ripple clock is not the best choose in FPGA design.

Thanks again, Brad.

Good luck.