Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Help with very small hold time violations

I am getting 50-100 ps negative hold slack on registers using the register feedback into the LUT. The launch and latch clock are the same, and the from and to node are also the same. The clock...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It should always be enabled. (I think the first release with this option had it disabled for some reason, but all new projects have it on.) It really applies to all domains. Even within a single domain, there will be a point where the clock tree branches, with one path going to the source register and the other branch going to the destination, and those branches will have ODV. But CCPP will add a lot more of this pessimism back in when it's a single clock domain, making the ODV much smaller(as it should be).