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Altera_Forum's avatar
Altera_Forum
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16 years ago

Help with very small hold time violations

I am getting 50-100 ps negative hold slack on registers using the register feedback into the LUT. The launch and latch clock are the same, and the from and to node are also the same. The clock...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You are correct. Enabling Common clock path pessimism removal fixed this timing error. Is there any time where this option should be turned on? It sounds like it is only useful for analyzing signals that cross clock domains.

I am using Quartus 9.0 Build 132.