Help with Using board-skew-parameter-tool

As the tool states, it's the delay from the FPGA ball to the first DIMM or device, like the highlight in your screen shot. If you were able to obtain the values for the DQ/DQS signals, I would think getting the trace lengths for the others would be no different, either in Hyperlynx or whatever board layout tool you use.

However, also note that this tool is not designed for Stratix IV, so I don't know if the numbers returned will be of any help in filling in the memory IP parameters for your design. You might have to manually run the calculations using the correct formulas in the UniPHY IP user guide.

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