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Altera_Forum
Honored Contributor
Honored Contributorhelp with TOP I/O management
Hello, I am student who recently got my hands on DE10-nano. Up until now I was always working with Artix-7, Xilinx board. What I am trying to do is to migrate some of my projects to Intel-Quart...
Altera_ForumHonored Contributor
Honored ContributorHi,
I also prefer the way Vivado does the pin assignments, but Quartus is also quite simple once you understood the concept. Without highlighting the many possible ways you could go, here's what I would recommend:- configure your Quartus project: select the correct FPGA, put in the VHDL files, select the top-level VHDL file
- in the main menu, go "Processing" -> "Start" -> "Analysis & Elaboration"
- once this ran successfully (i.e. no syntax errors or big logic errors), in the main menu go "Assignment" -> "Pin Planner"
- you'll see all I/O pins of your top level VHDL file in a table, as well as a graphical representation of the FPGA footprint; you can not drag&drop pads to signals, configure I/O standards, etc.
- close the Pin Planner, and run a full synthesis (main menu "Processing" > "Start Compilation")
