help with TOP I/O management

Hello,

I am student who recently got my hands on DE10-nano. Up until now I was always working with Artix-7, Xilinx board. What I am trying to do is to migrate some of my projects to Intel-Quartus. What I am now fighting is an assignments of TOP IO. In Vivado(overall Xilinx products) I had constraints, where there was a IO assignments available, so-called master.xdc files. Here I will post what I am used to work with and I would like to ask someone, if could tell me how to get the same result here in Quartus.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use ieee.fixed_pkg.all;

entity TOP is

Port (

JA1 : out STD_LOGIC; -- pwm

btnL : in STD_LOGIC; --debouncerL for state_machine - reset

clk : in STD_LOGIC

);

end TOP;

With this I can take oscilloscope and see the PWM if I connect it to JA1 pin.

In quartus I can't find how to assign this output lets say to pin GPIO_0 D1, because I really don't know how to declare it.

Can anyone please tell me how does this work in quartus. I have never been working with it and I think I am stuck with the Vivado way of doing thing and can't comprehend how does it work here.

Thank you.

IK