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Altera_Forum's avatar
Altera_Forum
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13 years ago

Help with this code

Hi, I've written a verilog code for a function that finds root by bisection method but unfortunately it's not giving the right output,maybe because of choice of variable. Can anyone please help me ou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm not a Verilog expert, but when you do 

xl=xm;
xu=xm;
You convert xm to integers, as xl and xu are integers. I assume this isn't what you wanted.

Do you intend to put it in an FPGA later? Then you can't use reals anyway, and you would have to clock the process and add some pipelining to avoid an overly complex and slow design.