Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Help with test bench error message

Hi, I'm new to vhdl and trying to simulate a counter from 0 to 3 using integers. The code that I used for the module is below library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Wow, I did not even realise that, thank you.

--- Quote Start ---

simple,

reset <= '0'; (you have written reset => '0')

at the end

--- Quote End ---