Altera_ForumHonored Contributor12 years agoHelp with test bench error message Hi, I'm new to vhdl and trying to simulate a counter from 0 to 3 using integers. The code that I used for the module is below library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL...Show More
Altera_ForumHonored Contributor12 years agosimple, reset <= '0'; (you have written reset => '0') at the end
Recent DiscussionsDuplicate_hierarchy_depth / duplicate_registerhow to reduce clock skew between synchronous clockQuartus - Users getting license Notification with new license appliedQuartus messages web search goes to IntelIs Quartus Prime Pro 22.4 Compatible with Stratix 10 NX Series Device 1SN21CEU2F55E2VG?