Altera_ForumHonored Contributor12 years agoHelp with test bench error message Hi, I'm new to vhdl and trying to simulate a counter from 0 to 3 using integers. The code that I used for the module is below library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL...Show More
Altera_ForumHonored Contributor12 years agosimple, reset <= '0'; (you have written reset => '0') at the end
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: