--- Quote Start ---
Kaz, We have the worst teacher for this subject, everyone relies on you tube and google for learning this.
I wanted to ask few more questions relating to the code if you don't mind:
The code is the following:
..snip..
--- Quote End ---
entity ripple_cnt isgeneric (ORDER: natural range 2 to 24:= 19);
-- What does this means. Order is of type generic or a keyword of somekind. Can I write Border instead of order?
-- Assuming it is not a keyword, the size of ORDER is 22 is that correct?
-- The value of order is 19, Correct? Is this value in binary 19?
-- "ORDER" is the identifier name, "natural range 2 to 24" is the type, just "natural" could also be used. You can change "ORDER" to "Border" if you want.
-- The range of ORDER is 23 different values.
-- ":= 19" defines a default value. When you instantiate the component in other VHDL code, you can change this value, or if you do not specify a value, 19 will be used.
port( fast_clk: in std_logic;
slow_clk: out std_logic);
end ripple_cnt;
architecture structure of ripple_cnt is
--internal signals
signal clks, count : unsigned(ORDER-1 downto 0);
-- I am confused, if I assume size of ORDER is 22, the ORDER-1 to 0 should give me size of 21 down to 0 but in my simulation window the clks and count are of the size 20 downto 0. Why is that?
-- I believe you need to look at the instantiation of the component in your testbench code. Are you changing the value of ORDER?
-- Looking at your last screenshot, the size of "clks" looks normal. ORDER = 19, so "clks" should be an STD_LOGIC_VECTOR(18 DOWNTO 0)
signal qs : unsigned(ORDER-1 downto 0):=(others=>'0');
-- Same question as above for this as well
begin
slow_clk <= qs(ORDER-1);
clks(0) <= fast_clk;
-- Cascade the FFs to implement Ripple Counter
clks(ORDER-1 downto 1) <= qs(ORDER-2 downto 0);
-- Implement Toggle FFs
ASYNCH_CNT: for i in 0 to ORDER-1 generate
-- What does generate do? I read about loop but don't know what generate means here?
-- Generate used with a for loop will instantiate one component several times.
-- It is useful since you can use the loop variable for clever things, and saves you some typing.
-- In this instance, that process statement is being generated ORDER number of times, with "i" changing each time.
T_FF:process(clks) is
begin
if rising_edge(clks(i)) then
qs(i) <= not qs(i); -- Implements a T_ Flip Flop
end if;
end process T_FF;
end generate;
end structure;
Hope this helps.
Honored Contributor
