--- Quote Start ---
In an async process, all signs must be assigned in ALL branches. In your code, LED_out is only assigned in the closed and opened states - it must also be assigned in all of the other states.
The way to avoid this is assign all signals in an asynchronous process a default value before the case statement. This way, if it is not assigned a specific value in a branch, it will take the default assignment.
process(state)
begin
output <= '0'; --default assignment
case state is
when state1 =>
--do something
--no assignment to output means it will be '0';
when state2 =>
output <= '1'; --overrides default assignment
when state3 =>
--no output assignment, output is '0' again
end case;
end process;
This way latches are avoided.
--- Quote End ---
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Hi Tricky, thanks for the tips it worked. Wow!! you guys are good, but i got another hitch can figure out what happened:
Error message when i tried the second time to compile it:
Error (125048): Error reading Quartus II Settings File C:/altera_trn/VHDL_uppgift_4e/VHDL_uppgift_4e.qsf, line 41
Info (125063): set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4e_vhd_tst " -section_id "VHDL_uppgift_4e_vhd_tst "
Error (125022): Section identifier missing or not required
Info (125063): set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst -section_id eda_simulation"
Info (125063): set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst " -section_id eda_simulation
Error (125022): Section identifier missing or not required
Info (125063): set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst -section_id eda_simulation"
Info (125063): set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst " -section_id eda_simulation
Error (125080): Can't open project -- Quartus II Settings File contains one or more errors
Error: Quartus II 64-Bit Hierarchy Elaboration was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 381 megabytes
Error: Processing ended: Thu Dec 12 12:47:21 2013
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:00
Is there a file i might not have added to settings > files > at the moment i just have the VHDL in place
Honored Contributor
