Hi guys, in my current setting i'm using a streaming mode FFT but thats just because it was the default setting. Another mode can help me get rid of serieus M4K-block issues. The system I have setup is like this: An external ADC is hooked on my Altera DE-1 board. The serial output of this ADC is put in a 12-bit bus and than stacked in a FIFO of 2048 words. When the FIFO is full, the FFT is activated and get's the 2048 samples. When this is done the ADC is activated again. Should I maybe use the burst, buffered burst mode of the FFT or just stick with streaming? Thanks in advance!

--- Quote Start --- Hi guys, in my current setting i'm using a streaming mode FFT but thats just because it was the default setting. Another mode can help me get rid of serieus M4K-block issues. The system I have setup is like this: An external ADC is hooked on my Altera DE-1 board. The serial output of this ADC is put in a 12-bit bus and than stacked in a FIFO of 2048 words. When the FIFO is full, the FFT is activated and get's the 2048 samples. When this is done the ADC is activated again. Should I maybe use the burst, buffered burst mode of the FFT or just stick with streaming? Thanks in advance! --- Quote End --- I am no expert on current altera fft (but used it a decade ago ! when it was one mode only and I converted it to streaming mode) . If indeed you can wait stopping the ADC then you can go for burst mode which requires minimum memory. If your ADC bursts are shorter than burst mode then you can go for buffer burst which uses some memory. If on the other hand you must keep ADC running always then you need to use streaming mode in which case you don't need pre-buffering as it is done inside fft using a lot of memory. To give you an idea about streaming that I did: I used two fft cores each running after the other plus memory for two frame buffering. first frame of input data was buffered completely then fft1 started meanwhile second frame was passed to its buffer. Once fft1 was done data was output and fft2 starts processing from its buffer while input passed to 1st buffer and so on. Now all this is done by choosing streaming mode avoiding all that trouble.

I'm getting very confused in how to use the FFT properly right now. I'm now using burst mode and a single output engine. I do get output from the FFT but when I use pythagoras on it (sqrt(real*real+imaginary*imaginary)) I get very high values. Sometimes with no audio input at all. My adc puts in a binary number around 127 with silence and goes up to 4096 as full number. Here is my code which is a state machine, which feeds the FFT. Please look at it and let me know what i'm doing wrong. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -------------------------------------- entity FFTStatemachine is port( clk,clk32mhz,reset,enable,deserializerdone: IN std_logic; enabledeserializer,writefifotestled,source_valid: OUT std_logic; fifoinput : IN STD_LOGIC_VECTOR (13 DOWNTO 0); fifooutput : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); source_real : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); source_imag : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); source_sop : OUT STD_LOGIC; source_eop :OUT STD_LOGIC ); end entity; -------------------------------------- architecture implementation of FFTStatemachine is component FFT is port ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; inverse : IN STD_LOGIC; sink_valid : IN STD_LOGIC; sink_sop : IN STD_LOGIC; sink_eop : IN STD_LOGIC; sink_real : IN STD_LOGIC_VECTOR (13 DOWNTO 0); sink_imag : IN STD_LOGIC_VECTOR (13 DOWNTO 0); sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); source_ready : IN STD_LOGIC; sink_ready : OUT STD_LOGIC; source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); source_sop : OUT STD_LOGIC; source_eop : OUT STD_LOGIC; source_valid : OUT STD_LOGIC; source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); source_real : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); source_imag : OUT STD_LOGIC_VECTOR (13 DOWNTO 0) ); end component; component FIFO is port ( rdclk : IN STD_LOGIC ; wrempty : OUT STD_LOGIC ; wrfull : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); rdempty : OUT STD_LOGIC ; rdfull : OUT STD_LOGIC ; wrclk : IN STD_LOGIC ; wrreq : IN STD_LOGIC ; aclr : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (13 DOWNTO 0); rdreq : IN STD_LOGIC ); end component; -- Signals & Variables -- ------------------------------------------------------------------- -- state definitions and signals ---------------------------------- ------------------------------------------------------------------- type state is ( Idle, WriteFIFO, FIFOLatency, Startreading, ReadFIFO, Finishreading, Finished ); signal present_state, next_state: state; signal enablefifolatencycounter: std_logic; signal enablefifosamplecounter: std_logic; signal FIFOlatencycounter: integer range 0 to 10:=0; signal fifocounter : integer range 0 to 3000:=0; signal done :std_logic; --FFT local input signals signal inverse : std_logic :='0'; signal sink_valid : std_logic; signal sink_sop : std_logic; signal sink_eop : std_logic; --signal sink_real : STD_LOGIC_VECTOR (11 DOWNTO 0); signal sink_imag : STD_LOGIC_VECTOR (13 DOWNTO 0):="00000000000000"; signal sink_error : STD_LOGIC_VECTOR (1 DOWNTO 0) :="00"; signal source_ready : STD_LOGIC; --FFT local output signals signal sink_ready : STD_LOGIC; --signal source_sop : STD_LOGIC; --signal source_eop : STD_LOGIC; --signal source_valid : STD_LOGIC; --FIFO local inputs signal enablewriting : STD_LOGIC; signal enablereading : STD_LOGIC; signal clearfifo : STD_LOGIC; --FIFO local outputs signal fifo_out :std_logic_vector (13 downto 0); signal readempty :std_logic; signal readfull :std_logic; signal writeempty :std_logic; signal writefull :std_logic; ---------------------------------------------------------------------- --PORTMAPS------------------------------------------------------------ ---------------------------------------------------------------------- begin FastFourierTransform: FFT PORT MAP (clk,reset,inverse,sink_valid,sink_sop,sink_eop,fifo_out,sink_imag,sink_error,source_ready,sink_ready,source_error,source_sop,source_eop,source_valid,source_exp,source_real,source_imag); FIFORAM : FIFO PORT MAP (clk,writeempty,writefull,fifo_out,readempty,readfull,clk32mhz,deserializerdone,clearfifo,fifoinput,enablereading); ------------------------------------------------------------------ -- sequential part of the statemachine ---------------------------- ------------------------------------------------------------------- fifooutput<=fifo_out; writefifotestled<=sink_ready; process(reset, clk, next_state) begin if (reset = '0') then clearfifo<='1'; present_state <= Idle; elsif (rising_edge(clk)) then clearfifo<='0'; present_state <= next_state; end if; end process; process(present_state,next_state, enable,sink_sop,fifocounter,done,writeempty,writefull,readempty,sink_ready,FIFOlatencycounter) begin case present_state is when Idle => if enable ='1' and writeempty = '1' then next_state <= WriteFIFO; else next_state <=Idle; end if; when WriteFIFO => if writefull ='1' then next_state <= FIFOlatency; else next_state <=WriteFIFO; end if; when FIFOlatency => if FIFOlatencycounter = 1 then next_state <= Startreading; else next_state <=FIFOlatency; end if; when Startreading => if sink_sop ='1' then next_state <= ReadFIFO; else next_state <=Startreading; end if; when ReadFIFO => if fifocounter = 511 then next_state <= Finishreading; else next_state <=ReadFIFO; end if; when Finishreading => if readempty ='1' then next_state <= Finished; else next_state <= Finishreading; end if; when Finished => if done = '1' and sink_ready = '1' then next_state <= Idle; else next_state <=Finished; end if; end case; end process; process(present_state,clk) begin case present_state is when Idle=> enablefifosamplecounter<='0'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='0'; sink_valid <='0'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; when WriteFIFO=> enablefifosamplecounter<='0'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='1'; enablewriting <='1'; enablereading <='0'; sink_valid <='0'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; when FIFOLatency=> enablefifosamplecounter<='0'; enablefifolatencycounter<='1'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='1'; sink_valid <='0'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; when Startreading=> enablefifosamplecounter<='1'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='1'; sink_valid <='1'; sink_eop <='0'; sink_sop <='1'; source_ready<='1'; when ReadFIFO=> enablefifosamplecounter<='1'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='1'; sink_valid <='1'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; when Finishreading=> enablefifosamplecounter<='1'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='1'; sink_valid <='1'; sink_eop <='1'; sink_sop <='0'; source_ready<='1'; when Finished=> enablefifosamplecounter<='0'; enablefifolatencycounter<='0'; done <='1'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='0'; sink_valid <='0'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; end case; end process; process(clk, enablefifosamplecounter,fifocounter) begin if(rising_edge(clk))and enablefifosamplecounter = '1' then fifocounter <= fifocounter+1; end if; if enablefifosamplecounter = '0' then fifocounter <=0; end if; end process; process(clk,enablefifolatencycounter,FIFOlatencycounter) begin if(rising_edge(clk))and enablefifolatencycounter = '1' then fifolatencycounter<=fifolatencycounter + 1; end if; if enablefifolatencycounter= '0' then fifolatencycounter <=0; end if; end process; end architecture;

The best way to check fft output is use an independent model e.g. matlab fft: y = fft(x,points); then round it as per fft core. The altera fft core wants you to use the output exponent to rescale the output for each block. Also check that your adc input is of correct format(2's complement) and that indeed you are inputting the values you think. Check that input frame is exactly entering the fft as required without any extra zeros or duplicate samples across the whole frame...etc.

I'm not familier with Matlab. Never used it before but I will see if I can get that package. For now I would like to try that exponent output. As far as I know I get a signed number out of the FFT, right? What should I do with the exponent number in combination with the real and imaginary output. I have read the FFT manual....but I do not really understand. By the way, the ADC gives out a straight binary of 12 bits, but I put 2 zero's in front of it and then put it in a 14 bit wide FFT. This will make it a signed binary.

Matlab may have free trial version. There is also has a free version called Octave. Or you may find other fft tools around. Alternatively you can inject one sample in the frame(otherwise set to zeros) and you should get a cosine/sine wave output at a given frequency(depending on sample location within frame). You can also reverse that by inputting a sine wave then you get a nozero sample surrounded by zeros. Scaling is well documented with example coding in the fft use guide. I don't really remember or know the details of the current core. I used to just shift divide my output by number of bits = exponent (as far as I remember). Note this is not a standard approach but done to the convenience of altera engineers, they have used internally a representation somewhere between 2's complement and standard floating point. Scaling of fft in general is not standardised across various tools so keep that in mind.

Help with FFT mode | Altera Community

22 Replies

Altera_Forum

Honored Contributor

13 years ago

second part:


257	200000	512	100390,625
258	200000	512	100781,25
259	200000	512	101171,875
260	200000	512	101562,5
261	200000	512	101953,125
262	200000	512	102343,75
263	200000	512	102734,375
264	200000	512	103125
265	200000	512	103515,625
266	200000	512	103906,25
267	200000	512	104296,875
268	200000	512	104687,5
269	200000	512	105078,125
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272	200000	512	106250
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274	200000	512	107031,25
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280	200000	512	109375
281	200000	512	109765,625
282	200000	512	110156,25
283	200000	512	110546,875
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285	200000	512	111328,125
286	200000	512	111718,75
287	200000	512	112109,375
288	200000	512	112500
289	200000	512	112890,625
290	200000	512	113281,25
291	200000	512	113671,875
292	200000	512	114062,5
293	200000	512	114453,125
294	200000	512	114843,75
295	200000	512	115234,375
296	200000	512	115625
297	200000	512	116015,625
298	200000	512	116406,25
299	200000	512	116796,875
300	200000	512	117187,5
301	200000	512	117578,125
302	200000	512	117968,75
303	200000	512	118359,375
304	200000	512	118750
305	200000	512	119140,625
306	200000	512	119531,25
307	200000	512	119921,875
308	200000	512	120312,5
309	200000	512	120703,125
310	200000	512	121093,75
311	200000	512	121484,375
312	200000	512	121875
313	200000	512	122265,625
314	200000	512	122656,25
315	200000	512	123046,875
316	200000	512	123437,5
317	200000	512	123828,125
318	200000	512	124218,75
319	200000	512	124609,375
320	200000	512	125000
321	200000	512	125390,625
322	200000	512	125781,25
323	200000	512	126171,875
324	200000	512	126562,5
325	200000	512	126953,125
326	200000	512	127343,75
327	200000	512	127734,375
328	200000	512	128125
329	200000	512	128515,625
330	200000	512	128906,25
331	200000	512	129296,875
332	200000	512	129687,5
333	200000	512	130078,125
334	200000	512	130468,75
335	200000	512	130859,375
336	200000	512	131250
337	200000	512	131640,625
338	200000	512	132031,25
339	200000	512	132421,875
340	200000	512	132812,5
341	200000	512	133203,125
342	200000	512	133593,75
343	200000	512	133984,375
344	200000	512	134375
345	200000	512	134765,625
346	200000	512	135156,25
347	200000	512	135546,875
348	200000	512	135937,5
349	200000	512	136328,125
350	200000	512	136718,75
351	200000	512	137109,375
352	200000	512	137500
353	200000	512	137890,625
354	200000	512	138281,25
355	200000	512	138671,875
356	200000	512	139062,5
357	200000	512	139453,125
358	200000	512	139843,75
359	200000	512	140234,375
360	200000	512	140625
361	200000	512	141015,625
362	200000	512	141406,25
363	200000	512	141796,875
364	200000	512	142187,5
365	200000	512	142578,125
366	200000	512	142968,75
367	200000	512	143359,375
368	200000	512	143750
369	200000	512	144140,625
370	200000	512	144531,25
371	200000	512	144921,875
372	200000	512	145312,5
373	200000	512	145703,125
374	200000	512	146093,75
375	200000	512	146484,375
376	200000	512	146875
377	200000	512	147265,625
378	200000	512	147656,25
379	200000	512	148046,875
380	200000	512	148437,5
381	200000	512	148828,125
382	200000	512	149218,75
383	200000	512	149609,375
384	200000	512	150000
385	200000	512	150390,625
386	200000	512	150781,25
387	200000	512	151171,875
388	200000	512	151562,5
389	200000	512	151953,125
390	200000	512	152343,75
391	200000	512	152734,375
392	200000	512	153125
393	200000	512	153515,625
394	200000	512	153906,25
395	200000	512	154296,875
396	200000	512	154687,5
397	200000	512	155078,125
398	200000	512	155468,75
399	200000	512	155859,375
400	200000	512	156250
401	200000	512	156640,625
402	200000	512	157031,25
403	200000	512	157421,875
404	200000	512	157812,5
405	200000	512	158203,125
406	200000	512	158593,75
407	200000	512	158984,375
408	200000	512	159375
409	200000	512	159765,625
410	200000	512	160156,25
411	200000	512	160546,875
412	200000	512	160937,5
413	200000	512	161328,125
414	200000	512	161718,75
415	200000	512	162109,375
416	200000	512	162500
417	200000	512	162890,625
418	200000	512	163281,25
419	200000	512	163671,875
420	200000	512	164062,5
421	200000	512	164453,125
422	200000	512	164843,75
423	200000	512	165234,375
424	200000	512	165625
425	200000	512	166015,625
426	200000	512	166406,25
427	200000	512	166796,875
428	200000	512	167187,5
429	200000	512	167578,125
430	200000	512	167968,75
431	200000	512	168359,375
432	200000	512	168750
433	200000	512	169140,625
434	200000	512	169531,25
435	200000	512	169921,875
436	200000	512	170312,5
437	200000	512	170703,125
438	200000	512	171093,75
439	200000	512	171484,375
440	200000	512	171875
441	200000	512	172265,625
442	200000	512	172656,25
443	200000	512	173046,875
444	200000	512	173437,5
445	200000	512	173828,125
446	200000	512	174218,75
447	200000	512	174609,375
448	200000	512	175000
449	200000	512	175390,625
450	200000	512	175781,25
451	200000	512	176171,875
452	200000	512	176562,5
453	200000	512	176953,125
454	200000	512	177343,75
455	200000	512	177734,375
456	200000	512	178125
457	200000	512	178515,625
458	200000	512	178906,25
459	200000	512	179296,875
460	200000	512	179687,5
461	200000	512	180078,125
462	200000	512	180468,75
463	200000	512	180859,375
464	200000	512	181250
465	200000	512	181640,625
466	200000	512	182031,25
467	200000	512	182421,875
468	200000	512	182812,5
469	200000	512	183203,125
470	200000	512	183593,75
471	200000	512	183984,375
472	200000	512	184375
473	200000	512	184765,625
474	200000	512	185156,25
475	200000	512	185546,875
476	200000	512	185937,5
477	200000	512	186328,125
478	200000	512	186718,75
479	200000	512	187109,375
480	200000	512	187500
481	200000	512	187890,625
482	200000	512	188281,25
483	200000	512	188671,875
484	200000	512	189062,5
485	200000	512	189453,125
486	200000	512	189843,75
487	200000	512	190234,375
488	200000	512	190625
489	200000	512	191015,625
490	200000	512	191406,25
491	200000	512	191796,875
492	200000	512	192187,5
493	200000	512	192578,125
494	200000	512	192968,75
495	200000	512	193359,375
496	200000	512	193750
497	200000	512	194140,625
498	200000	512	194531,25
499	200000	512	194921,875
500	200000	512	195312,5
501	200000	512	195703,125
502	200000	512	196093,75
503	200000	512	196484,375
504	200000	512	196875
505	200000	512	197265,625
506	200000	512	197656,25
507	200000	512	198046,875
508	200000	512	198437,5
509	200000	512	198828,125
510	200000	512	199218,75
511	200000	512	199609,375
512	200000	512	200000

Altera_Forum
Honored Contributor
13 years ago
I better explain fft output to you than answer your figures which are not clear to me:

N points fft output means N bins covering frequencies of +/- sampling frequency/2, (and usually indexed as 0 ~ N-1)

approximately:
bins 0~N/2 represent frequency range 0 ~ Fs/2 (Fs = sampling frequency sample/sec)
bins N/2+1 ~ N-1 represent frequency range -Fs/2 ~ 0
thus dc is at start and end(wrap up)
If your signal is real only then both halves get equal (mirror)
thus frequency of spectrum at point n: f(n) = Fs * n/N in Hz and its amplitude or phase is the value of amplitude or phase at n
amplitude = sqrt(Re^2 + Im^2) as you know

If you require fft results then use some simple vector e.g. constant, tell me your resolution and I will get you the result.
Altera_Forum
Honored Contributor
13 years ago
Thanks for your explain Kaz. That makes things a bit clearer.

I looked closely to the way I feed the FFT and came to the conclusion that my system is correct. I also now know that the output of the FFT is a block floating point and not a signed integer like I treated it. I now have to find a way to do my Pythagoras thing with this floating point. There is a mecacore function wich converts floating points to integers, but this function only works with 32-bit floats. I got a 14 bit mantissa from the FFT and a 5 bit exponent. I will have to look for a solution here.

Altera_Forum

Honored Contributor

13 years ago

I now got this:

I only need to sign extend it, any tips to do that?


mux:PROCESS(fftexp,fftvalid)
 -- VARIABLE  sel  :  STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
 -- sel := s1 & s0;   -- concatenate s1 and s0  
if (fftvalid = '1') then
 
  CASE fftexp IS
    WHEN  "110011"  => 
								full_range_real_out(26 downto 13) <= fftreal; --sll 13; -- -13
							   full_range_imag_out(26 downto 13) <= fftimag; --sll 13; -- -13
    WHEN  "110100"  =>  
	 
							   full_range_real_out(25 downto 12) <= fftreal; --sll 12; -- -12
							   full_range_imag_out(25 downto 12) <= fftimag;-- sll 12; -- -12
	 
    WHEN  "110101"  =>  
	 
							   full_range_real_out(24 downto 11) <= fftreal;-- sll 11; -- -11
						      full_range_imag_out(24 downto 11) <= fftimag; --sll 11; -- -11
	 
    WHEN  "110110"  =>  
								full_range_real_out(23 downto 10) <= fftreal;-- sll 10; -- -10
							   full_range_imag_out(23 downto 10) <= fftimag;-- sll 10; -- -10
	 
	 
	 WHEN  "110111"  =>  
								full_range_real_out(22 downto 9) <= fftreal; --sll 9; -- -9
							   full_range_imag_out(22 downto 9) <= fftimag; -- sll 9; -- -9
	 
	 WHEN  "111000"  =>  
	 
								full_range_real_out(21 downto 8) <= fftreal; --sll 8; -- -8
							   full_range_imag_out(21 downto 8) <= fftimag; --sll 8; -- -8
							  
	 WHEN  "111001"  =>  
								full_range_real_out(20 downto 7) <= fftreal; --sll 7; -- -7
						   	full_range_imag_out (20 downto 7)<= fftimag; --sll 7; -- -7
	 
	 WHEN  "111010"  =>  
	 
					    		full_range_real_out(19 downto 6) <= fftreal; --sll 6; -- -6
				 		      full_range_imag_out (19 downto 6) <= fftimag; --sll 6; -- -6
	 
	 WHEN  "111011"  =>  
								full_range_real_out(18 downto 5) <= fftreal; --sll 5; -- -5
							   full_range_imag_out(18 downto 5) <= fftimag; --sll 5; -- -5
	 
	 WHEN  "111100"  =>  
	 
								full_range_real_out(17 downto 4) <= fftreal; --sll 4 -- -4
							   full_range_imag_out(17 downto 4) <= fftimag; --sll 4; -- -4
							  
							  
	 WHEN  "111101"  =>  
								full_range_real_out(16 downto 3) <= fftreal; --sll 3; -- -3
								full_range_imag_out (16 downto 3)<= fftimag; --sll 3; -- -3
	 
	 WHEN OTHERS => 
  END CASE;
end if;
END PROCESS mux;

Altera_Forum
Honored Contributor
13 years ago
to sign extend say 12 to 16 bits:

data2 <= std_logic_vector(resize(signed(data1),16));

another note: for testing you can test Real and imaginary outputs directly (no need for old Pythogoras)

Altera_Forum

Honored Contributor

13 years ago

The code is complete, could you please verify if this is correct?

mux:PROCESS(fftexp,fftvalid)
 -- VARIABLE  sel  :  STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
 -- sel := s1 & s0;   -- concatenate s1 and s0  
if (fftvalid = '1') then
 
  CASE fftexp IS
    WHEN  "110011"  => 
								full_range_real_out(26 downto 13) <= fftreal ; --sll 13; -- -13
								full_range_real_out(12 downto 0) <= (OTHERS => '0');
								
							   full_range_imag_out(26 downto 13) <= fftimag; --sll 13; -- -13
								full_range_imag_out(12 downto 0) <= (OTHERS => '0'); --sll 13; -- -13
								
    WHEN  "110100"  =>  
								full_range_real_out(26)<=fftreal(13);
							   full_range_real_out(25 downto 12) <= fftreal; --sll 12; -- -12
								full_range_real_out(11 downto 0) <= (OTHERS => '0');
								
								full_range_imag_out(26)<=fftimag(13);
							   full_range_imag_out(25 downto 12) <= fftimag;-- sll 12; -- -12
								full_range_imag_out(11 downto 0) <= (OTHERS => '0');
	 
    WHEN  "110101"  =>  
								
								full_range_real_out(26 downto 25) <= fftreal(13) & fftreal(13);
							   full_range_real_out(24 downto 11) <= fftreal;-- sll 11; -- -11
								full_range_real_out(10 downto 0) <= (OTHERS => '0');
								
								
								full_range_imag_out(26 downto 25) <=fftimag(13) & fftimag(13);
						      full_range_imag_out(24 downto 11) <= fftimag; --sll 11; -- -11	
								full_range_imag_out(10 downto 0) <= (OTHERS => '0');
								
	 
    WHEN  "110110"  =>  
								full_range_real_out(26 downto 24) <= fftreal(13) & fftreal(13)& fftreal(13);
								full_range_real_out(23 downto 10) <= fftreal;-- sll 10; -- -10
							   full_range_real_out(9 downto 0) <= (OTHERS => '0');
								
								full_range_imag_out(26 downto 24) <=fftimag(13) & fftimag(13)& fftimag(13);
								full_range_imag_out(23 downto 10) <= fftimag;-- sll 10; -- -10
								full_range_imag_out(9 downto 0) <= (OTHERS => '0');
	 
	 
	 WHEN  "110111"  =>  
								full_range_real_out(26 downto 23) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13);
								full_range_real_out(22 downto 9) <= fftreal; --sll 9; -- -9
								full_range_real_out(8 downto 0) <= (OTHERS => '0');
								
								full_range_imag_out(26 downto 23) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13);
							   full_range_imag_out(22 downto 9) <= fftimag; -- sll 9; -- -9
								full_range_imag_out(8 downto 0) <= (OTHERS => '0');
								
	 WHEN  "111000"  =>  
								full_range_real_out(26 downto 22) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
								full_range_real_out(21 downto 8) <= fftreal; --sll 8; -- -8
							   full_range_real_out(7 downto 0) <= (OTHERS => '0');
								
							   full_range_imag_out(26 downto 22) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
								full_range_imag_out(21 downto 8) <= fftimag; --sll 8; -- -8
								full_range_imag_out(7 downto 0) <= (OTHERS => '0');
							  
	 WHEN  "111001"  =>  
								full_range_real_out(26 downto 21) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
								full_range_real_out(20 downto 7) <= fftreal; --sll 7; -- -7
								full_range_real_out(6 downto 0) <= (OTHERS => '0');
								
								
								full_range_imag_out(26 downto 21) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
						   	full_range_imag_out (20 downto 7)<= fftimag; --sll 7; -- -7
								full_range_imag_out(6 downto 0) <= (OTHERS => '0');
	 WHEN  "111010"  =>  
								full_range_real_out(26 downto 20) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
					    		full_range_real_out(19 downto 6) <= fftreal; --sll 6; -- -6
								full_range_real_out(5 downto 0) <= (OTHERS => '0');
								
								full_range_imag_out(26 downto 20) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
				 		      full_range_imag_out (19 downto 6) <= fftimag; --sll 6; -- -6
								full_range_imag_out(5 downto 0) <= (OTHERS => '0');
	 WHEN  "111011"  =>  
								full_range_real_out(26 downto 19) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
								full_range_real_out(18 downto 5) <= fftreal; --sll 5; -- -5
								full_range_real_out(4 downto 0) <= (OTHERS => '0');
								
								full_range_imag_out(26 downto 19) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
							   full_range_imag_out(18 downto 5) <= fftimag; --sll 5; -- -5
								full_range_imag_out(4 downto 0) <= (OTHERS => '0');
	 WHEN  "111100"  =>  
								full_range_real_out(26 downto 18) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
								full_range_real_out(17 downto 4) <= fftreal; --sll 4 -- -4
								full_range_real_out(3 downto 0) <= (OTHERS => '0');
								
							   full_range_imag_out(26 downto 18) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
							   full_range_imag_out(17 downto 4) <= fftimag; --sll 4; -- -4
						      full_range_imag_out(3 downto 0) <= (OTHERS => '0');
							  
	 WHEN  "111101"  =>  
								full_range_real_out(26 downto 17) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
								full_range_real_out(16 downto 3) <= fftreal; --sll 3; -- -3
								full_range_real_out(2 downto 0) <= (OTHERS => '0');
								
								full_range_imag_out(26 downto 17) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
								full_range_imag_out (16 downto 3)<= fftimag; --sll 3; -- -3
								full_range_imag_out(3 downto 0) <= (OTHERS => '0');
	 
	 WHEN OTHERS => 
  END CASE;
end if;
END PROCESS mux;

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
to sign extend say 12 to 16 bits:

data2 <= std_logic_vector(resize(signed(data1),16));

another note: for testing you can test Real and imaginary outputs directly (no need for old Pythogoras)
--- Quote End ---

I did'nt see you're comment in time. I now have done it manually
Altera_Forum
Honored Contributor
13 years ago
So Kaz, now I got these 2 huge vectors with the FFT's scaled real and imaginary data in. Now I have to Pythagoras them, right? But as what kind of format do I have to look at them?

Is it now an signed integer?
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
So Kaz, now I got these 2 huge vectors with the FFT's scaled real and imaginary data in. Now I have to Pythagoras them, right? But as what kind of format do I have to look at them?

Is it now an signed integer?
--- Quote End ---

yes once you do the scaling the values are signed 2's complement as input.
The output practically should not be that wide and you will need to observe the exponent as to what range is practical for your case then do some trimming on bits to fit fewer bits. You don't need to square it up to amplitude, you might just check each of real and imaginary directly.
Altera_Forum
Honored Contributor
13 years ago
I just put the real vector on the leds of the DE-1 board en saw that when I put music in, the leds are getting a bit nervous. This is a good thing I think. However, if I put our old Greek in. Amplitudes are the same af they were before scaling but now just a larger number.

Mind you, the only way I can test this is putting the result on the LEDs of the board because I have no Opencore IP license to do it in Modelsim.

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