Hi guys, in my current setting i'm using a streaming mode FFT but thats just because it was the default setting. Another mode can help me get rid of serieus M4K-block issues. The system I have setup is like this: An external ADC is hooked on my Altera DE-1 board. The serial output of this ADC is put in a 12-bit bus and than stacked in a FIFO of 2048 words. When the FIFO is full, the FFT is activated and get's the 2048 samples. When this is done the ADC is activated again. Should I maybe use the burst, buffered burst mode of the FFT or just stick with streaming? Thanks in advance!

--- Quote Start --- Hi guys, in my current setting i'm using a streaming mode FFT but thats just because it was the default setting. Another mode can help me get rid of serieus M4K-block issues. The system I have setup is like this: An external ADC is hooked on my Altera DE-1 board. The serial output of this ADC is put in a 12-bit bus and than stacked in a FIFO of 2048 words. When the FIFO is full, the FFT is activated and get's the 2048 samples. When this is done the ADC is activated again. Should I maybe use the burst, buffered burst mode of the FFT or just stick with streaming? Thanks in advance! --- Quote End --- I am no expert on current altera fft (but used it a decade ago ! when it was one mode only and I converted it to streaming mode) . If indeed you can wait stopping the ADC then you can go for burst mode which requires minimum memory. If your ADC bursts are shorter than burst mode then you can go for buffer burst which uses some memory. If on the other hand you must keep ADC running always then you need to use streaming mode in which case you don't need pre-buffering as it is done inside fft using a lot of memory. To give you an idea about streaming that I did: I used two fft cores each running after the other plus memory for two frame buffering. first frame of input data was buffered completely then fft1 started meanwhile second frame was passed to its buffer. Once fft1 was done data was output and fft2 starts processing from its buffer while input passed to 1st buffer and so on. Now all this is done by choosing streaming mode avoiding all that trouble.

I'm getting very confused in how to use the FFT properly right now. I'm now using burst mode and a single output engine. I do get output from the FFT but when I use pythagoras on it (sqrt(real*real+imaginary*imaginary)) I get very high values. Sometimes with no audio input at all. My adc puts in a binary number around 127 with silence and goes up to 4096 as full number. Here is my code which is a state machine, which feeds the FFT. Please look at it and let me know what i'm doing wrong. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -------------------------------------- entity FFTStatemachine is port( clk,clk32mhz,reset,enable,deserializerdone: IN std_logic; enabledeserializer,writefifotestled,source_valid: OUT std_logic; fifoinput : IN STD_LOGIC_VECTOR (13 DOWNTO 0); fifooutput : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); source_real : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); source_imag : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); source_sop : OUT STD_LOGIC; source_eop :OUT STD_LOGIC ); end entity; -------------------------------------- architecture implementation of FFTStatemachine is component FFT is port ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; inverse : IN STD_LOGIC; sink_valid : IN STD_LOGIC; sink_sop : IN STD_LOGIC; sink_eop : IN STD_LOGIC; sink_real : IN STD_LOGIC_VECTOR (13 DOWNTO 0); sink_imag : IN STD_LOGIC_VECTOR (13 DOWNTO 0); sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); source_ready : IN STD_LOGIC; sink_ready : OUT STD_LOGIC; source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); source_sop : OUT STD_LOGIC; source_eop : OUT STD_LOGIC; source_valid : OUT STD_LOGIC; source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); source_real : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); source_imag : OUT STD_LOGIC_VECTOR (13 DOWNTO 0) ); end component; component FIFO is port ( rdclk : IN STD_LOGIC ; wrempty : OUT STD_LOGIC ; wrfull : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); rdempty : OUT STD_LOGIC ; rdfull : OUT STD_LOGIC ; wrclk : IN STD_LOGIC ; wrreq : IN STD_LOGIC ; aclr : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (13 DOWNTO 0); rdreq : IN STD_LOGIC ); end component; -- Signals & Variables -- ------------------------------------------------------------------- -- state definitions and signals ---------------------------------- ------------------------------------------------------------------- type state is ( Idle, WriteFIFO, FIFOLatency, Startreading, ReadFIFO, Finishreading, Finished ); signal present_state, next_state: state; signal enablefifolatencycounter: std_logic; signal enablefifosamplecounter: std_logic; signal FIFOlatencycounter: integer range 0 to 10:=0; signal fifocounter : integer range 0 to 3000:=0; signal done :std_logic; --FFT local input signals signal inverse : std_logic :='0'; signal sink_valid : std_logic; signal sink_sop : std_logic; signal sink_eop : std_logic; --signal sink_real : STD_LOGIC_VECTOR (11 DOWNTO 0); signal sink_imag : STD_LOGIC_VECTOR (13 DOWNTO 0):="00000000000000"; signal sink_error : STD_LOGIC_VECTOR (1 DOWNTO 0) :="00"; signal source_ready : STD_LOGIC; --FFT local output signals signal sink_ready : STD_LOGIC; --signal source_sop : STD_LOGIC; --signal source_eop : STD_LOGIC; --signal source_valid : STD_LOGIC; --FIFO local inputs signal enablewriting : STD_LOGIC; signal enablereading : STD_LOGIC; signal clearfifo : STD_LOGIC; --FIFO local outputs signal fifo_out :std_logic_vector (13 downto 0); signal readempty :std_logic; signal readfull :std_logic; signal writeempty :std_logic; signal writefull :std_logic; ---------------------------------------------------------------------- --PORTMAPS------------------------------------------------------------ ---------------------------------------------------------------------- begin FastFourierTransform: FFT PORT MAP (clk,reset,inverse,sink_valid,sink_sop,sink_eop,fifo_out,sink_imag,sink_error,source_ready,sink_ready,source_error,source_sop,source_eop,source_valid,source_exp,source_real,source_imag); FIFORAM : FIFO PORT MAP (clk,writeempty,writefull,fifo_out,readempty,readfull,clk32mhz,deserializerdone,clearfifo,fifoinput,enablereading); ------------------------------------------------------------------ -- sequential part of the statemachine ---------------------------- ------------------------------------------------------------------- fifooutput<=fifo_out; writefifotestled<=sink_ready; process(reset, clk, next_state) begin if (reset = '0') then clearfifo<='1'; present_state <= Idle; elsif (rising_edge(clk)) then clearfifo<='0'; present_state <= next_state; end if; end process; process(present_state,next_state, enable,sink_sop,fifocounter,done,writeempty,writefull,readempty,sink_ready,FIFOlatencycounter) begin case present_state is when Idle => if enable ='1' and writeempty = '1' then next_state <= WriteFIFO; else next_state <=Idle; end if; when WriteFIFO => if writefull ='1' then next_state <= FIFOlatency; else next_state <=WriteFIFO; end if; when FIFOlatency => if FIFOlatencycounter = 1 then next_state <= Startreading; else next_state <=FIFOlatency; end if; when Startreading => if sink_sop ='1' then next_state <= ReadFIFO; else next_state <=Startreading; end if; when ReadFIFO => if fifocounter = 511 then next_state <= Finishreading; else next_state <=ReadFIFO; end if; when Finishreading => if readempty ='1' then next_state <= Finished; else next_state <= Finishreading; end if; when Finished => if done = '1' and sink_ready = '1' then next_state <= Idle; else next_state <=Finished; end if; end case; end process; process(present_state,clk) begin case present_state is when Idle=> enablefifosamplecounter<='0'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='0'; sink_valid <='0'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; when WriteFIFO=> enablefifosamplecounter<='0'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='1'; enablewriting <='1'; enablereading <='0'; sink_valid <='0'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; when FIFOLatency=> enablefifosamplecounter<='0'; enablefifolatencycounter<='1'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='1'; sink_valid <='0'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; when Startreading=> enablefifosamplecounter<='1'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='1'; sink_valid <='1'; sink_eop <='0'; sink_sop <='1'; source_ready<='1'; when ReadFIFO=> enablefifosamplecounter<='1'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='1'; sink_valid <='1'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; when Finishreading=> enablefifosamplecounter<='1'; enablefifolatencycounter<='0'; done <='0'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='1'; sink_valid <='1'; sink_eop <='1'; sink_sop <='0'; source_ready<='1'; when Finished=> enablefifosamplecounter<='0'; enablefifolatencycounter<='0'; done <='1'; enabledeserializer<='0'; enablewriting <='0'; enablereading <='0'; sink_valid <='0'; sink_eop <='0'; sink_sop <='0'; source_ready<='1'; end case; end process; process(clk, enablefifosamplecounter,fifocounter) begin if(rising_edge(clk))and enablefifosamplecounter = '1' then fifocounter <= fifocounter+1; end if; if enablefifosamplecounter = '0' then fifocounter <=0; end if; end process; process(clk,enablefifolatencycounter,FIFOlatencycounter) begin if(rising_edge(clk))and enablefifolatencycounter = '1' then fifolatencycounter<=fifolatencycounter + 1; end if; if enablefifolatencycounter= '0' then fifolatencycounter <=0; end if; end process; end architecture;

The best way to check fft output is use an independent model e.g. matlab fft: y = fft(x,points); then round it as per fft core. The altera fft core wants you to use the output exponent to rescale the output for each block. Also check that your adc input is of correct format(2's complement) and that indeed you are inputting the values you think. Check that input frame is exactly entering the fft as required without any extra zeros or duplicate samples across the whole frame...etc.

I'm not familier with Matlab. Never used it before but I will see if I can get that package. For now I would like to try that exponent output. As far as I know I get a signed number out of the FFT, right? What should I do with the exponent number in combination with the real and imaginary output. I have read the FFT manual....but I do not really understand. By the way, the ADC gives out a straight binary of 12 bits, but I put 2 zero's in front of it and then put it in a 14 bit wide FFT. This will make it a signed binary.

Matlab may have free trial version. There is also has a free version called Octave. Or you may find other fft tools around. Alternatively you can inject one sample in the frame(otherwise set to zeros) and you should get a cosine/sine wave output at a given frequency(depending on sample location within frame). You can also reverse that by inputting a sine wave then you get a nozero sample surrounded by zeros. Scaling is well documented with example coding in the fft use guide. I don't really remember or know the details of the current core. I used to just shift divide my output by number of bits = exponent (as far as I remember). Note this is not a standard approach but done to the convenience of altera engineers, they have used internally a representation somewhere between 2's complement and standard floating point. Scaling of fft in general is not standardised across various tools so keep that in mind.

Help with FFT mode | Altera Community

22 Replies

Altera_Forum
Honored Contributor
13 years ago
The big problem now is that I have to figure out a scale to put the amplitude bars on the screen. now, I got 219 pixels for full hight. Problem is I got no 0 point because with absolute silence the amplitude keeps fluctuate.

I can easily figure out the largest number possible and set that as 100% (219 pixels). But the problem is my starting off point.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
The big problem now is that I have to figure out a scale to put the amplitude bars on the screen. now, I got 219 pixels for full hight. Problem is I got no 0 point because with absolute silence the amplitude keeps fluctuate.

I can easily figure out the largest number possible and set that as 100% (219 pixels). But the problem is my starting off point.
--- Quote End ---

assuming your exponent scaling is correct(and I am not sure about the documentation so it might be correct) then I can see at least four lsbs always set at zero(out of 28 bits). Thus you can chop them off.
Moreover check the range of your exponent for your typical input and observe the MSBs. You will find some MSBs never change indicating you can remove them as well. Additionally you may control the original resolution of your fft.

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Help with FFT mode

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