Help with Error Messages

Question

Hi, this is my first time posting here. I just need some help figuring out how to correct my program. I'm new to VHDL. My assignment is to write VHDL coding to take information from ROM and output it to a video monitor. The 'ROM' is actually a mif picture stored in the same folder as the VHDL files. This picture is a 32 bit by 32 bit photo of an animal. The monitor is 640 x 480 pixels. The picture is to be written into part of the monitor. The rest of the monitor is to be black or just blank. This program is just to be simulated and not actually put on any hardware. The error messages are: Error (10500): VHDL syntax error at Homework7.vhd(28) near text "GENERIC"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at Homework7.vhd(33) near text ";"; expecting ":=", or "<="

Error (10500): VHDL syntax error at Homework7.vhd(34) near text ";"; expecting ":=", or "<=" The VHDL coding is attached. Thank you for your help, Mike

altera_forum · Answer

The generic clause is used set parameters of some component, like the number of bits of an input. For example:

entity incrementor is

generic(

WIDTH := 16

);

port(....

I modified version of the entity declaration may be:

ENTITY homework7 IS

PORT( clk, resetn : IN std_logic;

cs :IN std_logic;

address :IN std_logic_vector(9 DOWNTO 0);

q :OUT std_logic_vector(2 DOWNTO 0);

pixelout : OUT std_logic_vector(2 DOWNTO 0)

);

END homework7;

altera_forum · Answer

Thanks for your quick reply. The input "address" refers to a location in the picture.mif file. Also the output is supposed to be 3-bits and gives the pixel colors(I think). This whole part is to have only two inputs and one output. Won't setting it up the way you mention give it more inputs and outputs?

Thank you,

Mike

altera_forum · Answer

If I understand well address is an internal signal, the same with cs and q. So you are splitting your design in 2 aub-units. If so, this signals should not be visible in the entity declaration. Only appear below architecture/begin. Here you should instantiate 2 modules. One that output the pixelout signals ( and hsync and vsync ), and generates address. And the other module is the ram or rom storing the bitmap.

altera_forum · Answer

So, the signals address, cs, and q should be declared as in the following?

ENTITY homework7 IS

PORT (clk, resetn : IN std_logic;

pixelout : OUT std_logic_vector(2 DOWNTO 0));

END homework7;

ARCHITECTURE behavior OF homework7 IS

BEGIN

PROCESS

VARIABLE prow : INTEGER RANGE 0 TO 479 := 0;

VARIABLE pcol : INTEGER RANGE 0 TO 639 := 0;

VARIABLE count : INTEGER RANGE 0 TO 2 := 0;

VARIABLE address :IN std_logic_vector(9 DOWNTO 0);

VARIABLE cs :IN std_logic;

VARIABLE q :OUT std_logic_vector(2 DOWNTO 0);

VARIABLE paddress :std_logic_vector(9 DOWNTO 0):= "0000000000";

BEGIN

rom1: lpm_rom --megafunction to input data from picture

GENERIC MAP (lpm_width => 3, lpm_widthad => 10,

--3-bits per pixel

LPM_FILE => "picture.mif", --and 10-bit address

LPM_ADDRESS_CONTROL => "UNREGISTERED",

--for 1024 locations

LPM_OUTDATA => "UNREGISTERED")

PORT MAP(paddress => address, memenab => cs, q => q);

I do not know the correct way to use lpm_rom and read a particular address location. Currently I'm using 'paddress' and advancing that as in: paddress := paddress + 1;.

Thank you,

Mike

altera_forum · Answer

you cannot use an LPM rom inside a process. Components must be instantiated outside a process.

Forum Discussion

Help with Error Messages

9 Replies

Recent Discussions

Fitter stalls on "Advanced Physical Optimization" on Windows 10

NIOS V Sysnthesis Fails with Quartus 25.1 Lite

Known issues in Quartus Standard 18.0

Minimum pulse width violation on EMIF-HPS

CDC violations from DCFIFO