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Altera_Forum's avatar
Altera_Forum
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12 years ago

Help with Error Messages

Hi, this is my first time posting here. I just need some help figuring out how to correct my program. I'm new to VHDL. My assignment is to write VHDL coding to take information from ROM and output it...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If I understand well address is an internal signal, the same with cs and q. So you are splitting your design in 2 aub-units. If so, this signals should not be visible in the entity declaration. Only appear below architecture/begin. Here you should instantiate 2 modules. One that output the pixelout signals ( and hsync and vsync ), and generates address. And the other module is the ram or rom storing the bitmap.