help with counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

entity ledwithcounter is

port( GPIO_0 : in std_logic_vector(1 downto 0);

ld_enb : in std_logic;--parallel load enable,active high

clk : in std_logic;-- system clock

cnt_enb : in std_logic;--count enable, active high

rst_n : in std_logic;-- reset,active high

cnt_out : out std_logic_vector(1 downto 0);

q : out std_logic_vector(1 downto 0));

end ledwithcounter ;

architecture bufferwithGpio_arc of ledwithcounter is

begin

process(GPIO_0)

begin

if (GPIO_0(0)='1') then q<=GPIO_0(1 downto 0);

else q<= "00";

end if;

end process;

end bufferwithGpio_arc;

architecture rtl of counterun is

begin

-- Local signal because it has to be read internally

-- unsigned type used because of "+" operation needed

signal count: unsigned(1 downto 0) := "00";

begin -- architecture rtl

counter:process(clk,rst_n)

begin

if ( rst_n='0' ) then

count <=(others=>'0');

elsif(clk'event and Clk ='1')then

if (ld_enb='1')then

count<=GPIO_0;

elsif(cnt_enb ='1')then

count <=count+1;

end if;

end if;

end process counter;

-- assigment ouput

cnt_out <= std_logic_vector(count);

end architecture rtl;

i have follow all of your instruction.but stil there is error occur.Error (10500): VHDL syntax error at ledwithcounter.vhd(31) near text "signal"; expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement....

do i need to declare the port of my counter in separate ways from my input port. need clarifaication sir..