Honored Contributor
Honored ContributorHi Bootstrap -
I like your DirectX comment. You might like WYSIWYG cells. You set the function as a truth table and a few switches, hook up inputs, and it goes in one cell unless completely illegal. WYSIWYG is to assembly as primitives are to (strange compiler pragmas). There are WYSIWYG CRCs of various common widths for Stratix II (wrong chip, but a good demo) at these links - www.altera.com/literature/manual/cookbook.zip www.altera.com/literature/manual/stx_cookbook.pdf In the ZIP under crc/xor6.v is a little cell building block. The truth table is 6996... which you may recognize as a hex XOR pattern. crc_register.v has the "registered 2:1 mux" type building block you mentioned earlier. The tools will have no freedom to (e.g. move the synchronous clear AND gate out into the LUT). These CRC's are hard factored for minimum depth on 6 LUT parts. It sounds like you've already figured out how to do the pattern for minimum depth on 4's. To port from Stratix II to C3 I think you can just change "stratixii_lcell_ff" to "cycloneiii...", delete the extra LUT inputs, and shorten the truth tables to 16 bit. Let me know if you want to go there. I can explain the nitty gritty in more detail.
