Honored Contributor
Honored Contributor---- second half of message -----
You said, "If you limit the logic in front of the LCELL primitive to what will fit in a single LUT, then you can essentially create each LUT yourself.". I worry this will not suffice. For example, consider the component I described in my original message. To implement this with components available in Quartus2 would end up having 3~4 levels of components in a serial = sequential configuration. 1: compute two values: (A ^ B) and (A = unmodified) 1a: output AXORB = A ^ B 1b: output A = A 2: multiplexer selects one of two input values based upon low 2 bits of xcounter 2a: xcounter = 0 or 1 or 2 ::: route signal A to output 2b: xcounter = 3 ::: route signal AXORB to output 3: register computed result 3a: output of multiplexer routed to input of register 3b: when CLK rises, capture value at register input pin and output from register 4: LCELL 4a: output of register routed to input of LCELL 4b: input of LCELL routed to output of LCELL Now, I understand that LCELL may in fact be a fictional device for Quartus2, and therefore hopefully is not an real LE/LUT/buffer/register/anything on the FPGA. But, assuming that is true, what LCELL "sees" feeding it is - *one register* --- THAT IS ALL. You see, this is one major problem with the design of Quartus2 (in my not-humble-enough but admittedly newbie opinion). I would have included an optional "registered output" on every single component. After all, the registered output is in every single LE, and in the synchronous designs we want to [and almost need to] design with, the need for registered output is very, very common. Instead, Quartus2 forces us to add hundreds of 8ffxx or 74374 packages all over out schematics, which bloats and confuses them horribly. You see the problem? How many levels back does the LCELL "look" for opportunities to merge levels together? Even if the answer is "many levels", it is not always possible to find components that allow the designer to express the functionality in ways Quartus2 will be able to detect the merge possibilities. Give us LE4 components and "problem solved". You say that the largest part of designs do not need to be designed this "low level way". True enough - sometimes the components offered express the design reasonably well. Some sections of an FPGA run much faster than required, so inefficient implementation of LEs has no consequences (unless you happen to ooze beyond the size of your FPGA). However, only the smallest trivial designs are not massively expanded into huge chaotic mess of utterly pointless components. I mean really, why fill up tons of space with 4 more 74374 components --- when you could have run a CLK line into the logic that feeds them? This single monstrous bloatocracy is repeated *endlessly* in Quartus2 schmatics - even though the output of every LE in the FPGA can be registered or not. I am painfully aware of my status is "total newbie" (almost "newborn" you might say) and therefore any claim of "stupid design" from my fingertips is likely to be smashed flat by heavy sledgehammers of experience. Nonetheless, I will take the risk and venture to provisionally call this omission "absurd" (and save "stupid" for next time - hopefully not). But understand this. My only purpose of "tweaking" someone with opinions like "absurd" --- is to get myself squashed to atomic scale when some expert (?Quartus2 designer?) shows me how to do what I need, or tells me why my desired approach is even dumber than stupid. Either way, then I'll know how to move forward efficiently (with or without FPGAs). I am not sure how to answer your last two paragraphs concisely or comprehensibly. I freely admit to being on the "fringe" in terms of how I design hardware and software. Specifically, I *do* "sweat the details" more than most designers. Every time I try the conventional (lazy) ways that other developers advocate, I get trashed one way or another. I have learned, from long, hard, nasty, painful experience to "trust no one". Almost every time I tried to avoid understanding or implementing the low-level internal details, I was terminally shafted --- I had to either "abandon project" or "start all over" or at least "ditch their high-level component and implement everything myself". And this gets worse every year, as more "implementors/sellers" adopt the bogus/corrupt/hostile philosophy (rationalization) of "let the buyer beware". They mislead us to believe their product will do everything you want and more, and do so better and faster than you can even imagine. It has gotten so bad (slowly, so people just accept it as "normal") that I see many design engineers and groups fail time after time after time, while I succeed time after time after time. Yet they never stop telling me how stupid I am for insisting that I must understand every detail of every nook and cranny of my designs, and adopting what I call me "all things considered" approach to product design. They honestly admit their amazement that I finish projects so fast and so well, but when I ask how that is consistent with their endless claims I do everything in stupid and inefficient ways, they just shrug. This is my way of saying, I honestly don't know what you propose. When you say I should take a high-level view, do you mean I should draw a big rectangle with inputs and outputs and label it "compute CRC32"? If so, I have done exactly that --- but that is my block diagram. Unless Quartus2 has achieved human-level++ consciousness, I am quite sure it cannot convert this block into a complete working interconnect of LEs!!! Or can it? And if I put "timing constraints" on the inputs and ouputs of this block diagram, how does this help Quartus2 know what logic belongs inside the block? I am missing something. Whenever I have first conversations like this with other designers, we always find each other talking from another dimension in the twilight zone (or at least "on another page"). BTW, in my view, what I propose is trying to move TOWARDS the higher-level. Is that not true - in your opinion? Consider this. If I combine several elements (XOR, multiplexer, register, etc) into one single coherent logical functional entity --- is this not exactly what you refer to as "higher level"? If so, this is exactly what I wish to do, what I am trying to find ways to do in Quartus2 - to design at the higher "logical" level. It seems like I should be able to do this, and I still suspect some Quartus2 expert will jump in and tell me how it can be done, and where to find the magic pulldown menus. Are you listening, sir Quartus2 developer :cool: sir? Please help this neandrathal! ----- the end -----
