help: where is "LE" or "LUT" component (or "how do I create my own components?")

Brad. This reply slightly exceeds the 10000 character limit, so I most post two messages.

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I inserted an LCELL into my schematic, but it has only one input and one output, so the LCELL certainly is not a LE or LUT or LAB component itself. I read all the help about LCELL in the integrated Quartus2 help system, but do not understand how it helps me.

I sorta more-or-less understand your description of LogicLock, I think. However, to the extent I do understand what you say about LogicLock, it only solves half my problem, and not the most annoying half. I refer to the "exploding schematics" problem, where nice neat compact schematics explode into enormous badly organized tangled messes.

If I understand your description of LogicLock, I can effectively draw a boundary around a group of components on my huge messy outta-control schematic --- and tell Quartus to treat this like a single component or minimum number of components to the degree possible (obviously wires come in and go out).

Perhaps this encourages Quartus2 to merge components within the LogicLock domain to the degree possible before it performs the general merge attempts across a whole design. This does increase the probability the components the designer wants together are in fact put together - but I very much doubt it can assure this. Are you sure Quartus2 will combine the three elements of my example into one LE/LAB --- the 16-bit XOR functionality with the 4-to-1 multiplexer functionality with the output register functionality? Perhaps, but even though I am a total newbie FPGA designer, I designed several CPUs and other large devices (yes, from hundreds of gates and simple MSI like muxes), so I tend to give weight to my impression that my entire design will be impractical because the speed of this part of the design is insufficient --- EXACTLY BECAUSE --- these three components are not combined in the way I require. And I can tell you, with total certainty, that designing with FPGAs shall meet an instantaneous, unfortunate, unnecessary and possibly permanent end at our product development organization *if* that happens and *if* I cannot find a way to force Quartus2 to do what I *should* be able to tell it in the first place (make these components into one LE or LAB (one LE per bit in each bus involved)).

Please, do not read an arrogant tone into the above. I am simply trying to describe what must happen in this particular case. We have an FPGA that (I am very confident) is capable and fast-enough to do the work we require of it, but we seem to have found we are in danger of being told our design is "not fast enough" [to run in our chosen part]. The problem with that is - I have checked prices, and we cannot afford the cost of the next fastest version of the EP3C5F256 chip (and certainly not the fastest version).

Therefore, I still believe I may have a valid point. That point is, essentially, that Altera will lose some smallish but non-trivial percentage of FPGA sales because of one small, trivial-to-implement but extremely fundamental feature is missing from Quartus2. Altera could probably implement the solution in a few different ways, but *certainly* the most friendly way is the following:

Proposal: Make the following change to Quartus2 (at least in the schematic entry mode): Add the following components: LE4, [LAB]. The functionality of the LE4 is exactly equal to the current standard LEs (logic elements) that comprise the vast majority of current FPGA chips (cyclone3 for example). The schematic package looks like this:

inputs: A,B,C,D - these are variable mix of data-inputs and control-inputs

inputs: CLK - captures the output of the LUT on rising edge

inputs: ENA - enables the CLK signal

inputs: REG - selects registered output (otherwise the LUT output leaves the LE)

inputs: ACL - asynchronous clear (only if definitely always available in every LE situation)

inputs: ??? - any other inputs that are practical to [optionally/sometimes] support

outputs: OUT - direct output of LUT or registered output of LUT

mode: any practical mode settings would be set in a dialog box, presumably to tell the LE to reconfigure the LUT from the normal (4:1) mode to the (2x 3:1 + 2:1) mode and so forth (to handle less-common functionality such as carry-in / carry-out, shift-in / shift-out, and so forth).

Note: If any less-common functionality requires excessive kludge or confusion to this LE4 component, the appropriate response is to omit that functionality - do not fail to implement the LE4 and LAB just because some minor functionality is not convenient to represent.

I do not see the LAB component as an actual component, really. I just say the term LAB to imply the Quartus2 should happily create and/or merge side-by-side identical LE4s, in exactly the way Quartus2 does for many other components. If Quartus2 does not support a way to merge any arbitrary number of identical LE4s into a single package/component, then at least support groups of 4, 8, 16, 32 [and 64].

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