help: where is "LE" or "LUT" component (or "how do I create my own components?")

For software in a language like C, the compiler creates the machine code. The compiler gives you the ability to insert some assembly statements where you really need low-level control. Similarly, FPGA compilers start with HDL or schematics to create the LUTs, registers, LABs, etc. while giving you some low-level control for those situations when you really need it.

If you insert an LCELL primitive, that will tell Quartus to make the combinational signal at the LCELL primitive be the output of a LUT. If you limit the logic in front of the LCELL primitive to what will fit in a single LUT, then you can essentially create each LUT yourself.

The Fitter will combine LUTs with registers to create LEs or ALMs. To tell the Fitter which LEs or ALMs to put in one LAB, use a LogicLock region that is one LAB in size. To tell the Fitter to put LEs or ALMs into a particular LAB, you can use a LAB location assignment.

It is rare to need to design at this low level. Most designs don't require it, and those that do usually require it for only a tiny portion of the design.

First try describing your design at a higher level of abstraction and giving Quartus complete timing constraints. If you don't get the area or timing results you need after doing all the normal things first to help Quartus optimize the design, then you can tweak portions of the design that need manual control.