Help: What's the difference between functional simulation and timing one

The circuitry you're describing concerns me in that it will be difficult to do static timing analysis on. Note that I would generally recommend to:

1) Not do gated clocks, i.e. divide them down and use ripple clocks. Instead use a PLL to divide the clock down or use the higher speed clock and have your logic create clock enables rather than higher speed clocks. Ideally you want to have as few clocks as possible, and keep them edge aligned(all outputs of the same PLL or based off a single base clock), so you don't have to worry about hold analysis.

2) I wouldn't use the asynchronous ports of the register to perform logic. Instead, they should just be used as a system set/reset.

Note that these are recommendations. Plenty of designs have broken these recommendations and work perfectly fine, but I find that often users do these things when they never really had to, and they find themselves unable to do static timing analysis(mainly because they don't understand how to constrain it). I've found these rules get broken more often than not in schematics because it's easy to do. Something happens on the output of a register and you want that signal to allow some other register to do something. So you tie it to the clock or asynch port of that register, rather than the clock enable. I know you don't want to go back and redo the design, but I'm just throwing these out there as a possibility.