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Altera_Forum
Honored Contributor
18 years agoHi ,Rysc.Thank you very much.
You're all right. There do exist some problems in my project. I designed a random-phase clock management. There are five parts in my designs, the first part ,an N divider and a dff,it provides the clk needed in native circuits; the second one,a phase detector,it detects clk's rising event and data' falling event when data'phase is in front of clk',otherwise when clk'phase is forward,it detects data's rising event and clk' falling event ,then the detector sends the signal to the third part---a counter. The system provides global clk to the counter ,and then counter will send the number to a comparator ,which has been set an initial number(N/2),it provides three typical signals to first part and control the native clk(add or deduct one global clk circle) I examined my projects ,the problem may exist in second part.There are two parts ,datalate and databefore ,they all contain two dff, i use the clk'rising event to sample the data'rising event and use the data'rising event to sample the clk'rising event.