Help: What's the difference between functional simulation and timing one

One thing I wanted to add to this thread - First, if you don't have timing requirements in your design, I suggest adding them. It's not necessarily what is wrong between the simulations, but this is a recommended step for all designs(constraining them). Without constraints, the fitter doesn't know what to do, and more importantly, there is no way for the back-end timing analysis to let you know if you passed or failed your requirements, since there are no requirements to begin with.

Second, although it's useful to understand the differences between a functional and timing simulation, I wouldn't try to fix the problem yet without diving deeper into why your timing simulation is failing. It can be a painful process, but at some point there is a register transfer where you expect something to happen, and something else happens. Once you find this, you can analyze why this didn't occur(is there an error in my code? Is the datapath too long for my clock rate? Etc.) Although it takes time to isolate the issue like this, it makes the fix much easier since you have a solid understanding of what you're trying to fix.