Help: What's the difference between functional simulation and timing one

Also the hashed white line would indicate that you are driving a "weak" high or low signal. If you move your cursor over the signal where the white hashed line is then the simulater window will show a 'H' or 'L' signal.

Regarding you timing simulation you will need to make sure that once the SDF is back annotated onto the netlist which is done something similar to the following

vsim -t ps -sdftyp tb_top/top_blk/=../../TOP/NETLIST/TOP_vhd.sdo TOP_TB_LIB.tb_top

the clock from the testbench should not be edge-aligned with the data as this would not satisfy the set-up requirement of the flip-flops and 'X' 's will be propagated in your design

Hope this helps